1. Field of the Invention
The present invention generally relates to semiconductor packages and manufacturing methods of the semiconductor packages. More specifically, the present invention relates to a semiconductor package including a semiconductor device, and a wiring board and a manufacturing method of the semiconductor device.
2. Description of the Related Art
Conventionally, a semiconductor package where a semiconductor device is mounted on a wiring board has been known. FIG. 1 is a cross-sectional view partially showing a related art semiconductor package. As shown in FIG. 1, a semiconductor package 300 includes a semiconductor device 400 and a wiring board 500. The semiconductor device 400 includes a semiconductor substrate 410, electrode pads 420, and connecting terminals 430.
A semiconductor integrated circuit (not shown in FIG. 1) and others are formed on the semiconductor substrate 410. Silicon or the like, for example, can be used as a material of the semiconductor substrate 410. The connecting terminal 430 as an electrode is formed on the electrode pad 420. A solder bump or the like, for example, can be used as the connecting terminal 430.
The wiring board 500 includes an insulation layer 530, a wiring layer 540, and a solder resist layer 550. In the wiring board 500, the wiring layer 540 is formed on the insulation layer 530. The solder resist layer 550 having opening parts 550x is formed on the wiring layer 540. Cu or the like, for example, can be used as the wiring layer 540. As the insulation layer 530, for example, epoxy group resin, glass epoxy where glass fiber cloth is included in the epoxy group resin, or the like can be used.
The connecting terminals 430 of the semiconductor device 400 are electrically connected to portions exposed via the opening parts 550x of the wiring layer 540 of the wiring board 500. See, for example, Japanese Laid-Open Patent Application Publication No. 2008-153340 and Japanese Laid-Open Patent Application Publication No. 2009-16773.
In the meantime, the coefficient of thermal expansion of glass epoxy, which can be used as the insulation layer 530, is approximately 18 ppm/° C. The coefficient of thermal expansion of silicon, which can be used as the semiconductor substrate 410, is approximately 3 ppm/° C. Due to such a difference of the coefficients of thermal expansion, when heat is applied to the semiconductor package 300, the wiring board 500 is warped more than the semiconductor substrate 410. Therefore, stress may be generated at a connecting part in the vicinity of the connecting terminal 430, the connecting part being configured to connect the semiconductor substrate 410 and the wiring board 500 to each other. Cracks may be generated at an interface between the connecting terminal 430 and the wiring layer 540 or at a part of the semiconductor substrate 410 in the vicinity of the connecting terminal 430.